Title :
Low-power decimation filters for oversampling ADCs via the decorrelating (DECOR) transform
Author :
Dongwon See ; Shanbhag, Naresh R. ; Feng, Milton
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
The area and power consumption of oversampling analog-to-digital converters (ADCs) are governed largely by the associated digital decimation filter. This paper presents a low power, area-efficient digital decimation filter for an oversampling ADC application that employs the decorrelating (DECOR) transform in order to reduce the power dissipation and area. The DECOR transform exploits the correlation in the coefficients and data sequences to reduce the precision. Simulation results indicate that a decorrelated 8192-tap decimation filter with a decimation ratio of 64 results in a reduction of 5 bits in the coefficient and accumulator size. This corresponds to savings in complexity of 25%. In multi-stage decimation filters, it is shown that the decimation ratio of the last stage needs to be greater than 4 for DECOR to be useful
Keywords :
analogue-digital conversion; decorrelation; digital filters; low-power electronics; accumulator size; area-efficient digital decimation filter; data sequences; decimation ratio; decorrelating transform; low-power decimation filters; multi-stage decimation filters; oversampling ADCs; power dissipation; Analog-digital conversion; Decorrelation; Delta modulation; Digital filters; Energy consumption; Finite impulse response filter; Frequency; Low-frequency noise; Noise shaping; Transfer functions;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.855982