Title :
A novel low jitter PLL clock generator with supply noise insensitive design
Author :
Yijing, Lin ; Shimin, Sheng
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
A novel control circuit is proposed to suppress the jitter caused by high frequency noise, which spectrum is beyond the loop bandwidth of the PLL used as clock generator in an USB2.0 application. Hspice simulates the circuits with BSIM3V3 model, and the cycle-to-cycle jitter is 1.68 ps when the VDD noise is 200 mv, 10 MHz square wave
Keywords :
SPICE; circuit noise; clocks; jitter; phase locked loops; BSIM3V3 model; HSPICE simulation; PLL clock generator; USB2.0; control circuit; high-frequency noise; jitter suppression; supply noise insensitive design; Circuit noise; Clocks; Frequency; Jitter; Low-frequency noise; Noise generators; Phase locked loops; Phase noise; Voltage-controlled oscillators; Working environment noise;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982547
