An 8-bit 125 MHz folding and interpolating analog-to-digital converter

Author

Guo, Xinwei ; Chen, Cheng ; Ren, Junyan

Author_Institution

ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China

fYear

2001

fDate

2001

Firstpage

293

Lastpage

295

Abstract

A CMOS folding and interpolating analog-to-digital converter fully compatible with standard digital CMOS technology is described. Offset averaging reduces the input capacitance. Dynamic distributed sample-and-hold improves the dynamic performance of the A/D converter. Current-mode, fully differential and open-loop analog circuitry is used to achieve high speed. An 8-bit 125 MHz A/D converter with 100 MHz input bandwidth is realized in standard 0.35 um 3.3 V CMOS technology

Keywords

CMOS integrated circuits; analogue-digital conversion; current-mode circuits; high-speed integrated circuits; interpolation; low-power electronics; sample and hold circuits; 0.35 micron; 100 MHz; 125 MHz; 3.3 V; 8 bit; CMOS folding and interpolating analog-to-digital converter; current-mode fully-differential open-loop analog circuit; dynamic distributed sample-and-hold technique; input bandwidth; input capacitance; low-power high-speed operation; offset averaging; Analog-digital conversion; Bandwidth; Binary codes; CMOS technology; Capacitance; Circuits; Differential amplifiers; Preamplifiers; Resistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982556

Filename

982556