Clock and data recovery circuit for 2.5Gbps Gigabit Ethernet transceiver

Author

Li, Shuguang ; Ren, Junyan ; Yang, Lianxing ; Ye, Fan ; Zhang, Y. M Michael

Author_Institution

ASIC, Fudan Univ., Shanghai, China

fYear

2001

fDate

2001

Firstpage

330

Lastpage

332

Abstract

This paper describes a clock and data recovery circuit that operates at 2.5Gb/s in a 1.8V 0.18um digital CMOS technology. It is a main part of the receive path in a fully integrated CMOS SerDes transceiver. A frequency-aided PLL-based dual-loop architecture is adopted. To suppress the noise, a ring oscillator composed of differential buffer delay stage is introduced that employs some technique to lower the gain. A special data-triggered phase/frequency detector is also described. A transistor-level simulation shows the overall lock behavior

Keywords

CMOS digital integrated circuits; digital phase locked loops; local area networks; synchronisation; transceivers; 0.18 micron; 1.8 V; 2.5 Gbit/s; CMOS SerDes transceiver; Gigabit Ethernet transceiver; clock and data recovery circuit; data-triggered phase/frequency detector; differential buffer delay stage; digital CMOS technology; frequency-aided PLL-based dual-loop architecture; noise suppression; ring oscillator; transistor-level simulation; CMOS digital integrated circuits; CMOS technology; Clocks; Delay; Ethernet networks; Frequency; Integrated circuit technology; Phase detection; Ring oscillators; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982567

Filename

982567