Area estimation of LUT based designs

We present an area estimator of LUT (look up table) based designs. Our estimator takes in a structural VHDL description and estimates the upper and lower bounds of number of look-up tables needed in FPGA based design. Through estimation process, Espresso Boolean Minimizer is used to get the minimized netlist. Number of literals and cubes are extracted. A number of well known techniques for LUT estimation is integrated to get the bounds as a function of the extracted number of literals and number of cubes. The proposed technique is fast and accurate enough to build an online estimator which predicts the size while the designer is editing the description to early justify the complexity of different architectures.