Interconnect layout macromodelling and simulation in high speed circuits

Author

Kaufmann, N. ; Konczykowska, A.

Author_Institution

Groupement d´´Interet Econ., OPTO+, Marcoussis, France

Volume

3

fYear

2000

fDate

2000

Firstpage

125

Abstract

This paper deals with the layout problems of VHSICs. It shows how parasitic influence of the interconnects on the global circuit performance can be selectively taken into account. The method is based on the layout extraction coupled with a model library of basic forms. Hierarchical symbolic analysis is proposed to create macromodels and speed up the calculation. An example of 40 Gb/s driver design illustrates the presented approach

Keywords

circuit layout CAD; circuit simulation; integrated circuit interconnections; integrated circuit layout; integrated optoelectronics; symbol manipulation; very high speed integrated circuits; 40 Gbit/s; VHSICs; circuit simulation; driver design; global circuit performance; hierarchical symbolic analysis; high speed circuits; interconnect layout macromodelling; layout extraction; layout problems; model library; Circuit simulation; Coplanar waveguides; Driver circuits; Frequency; Integrated circuit interconnections; Libraries; Microwave circuits; Optical fiber communication; Solid modeling; Very high speed integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856012

Filename

856012