DocumentCode
2225648
Title
HDL filter for optimized area-delay minimization in FPGA synthesis
Author
Wahba, Ayman M.
Author_Institution
Ain Shams University
fYear
2004
fDate
5-7 Sept. 2004
Firstpage
43
Lastpage
46
Keywords
Area measurement; Circuit synthesis; Delay; Field programmable gate arrays; Filtering; Filters; Hardware design languages; Logic; Minimization; Signal synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical, Electronic and Computer Engineering, 2004. ICEEC '04. 2004 International Conference on
Print_ISBN
0-7803-8575-6
Type
conf
DOI
10.1109/ICEEC.2004.1374376
Filename
1374376
Link To Document