An error-controlled methodology for approximate hierarchical symbolic analysis

Author

Guerra, O. ; Rodríguez-Garcia, J.D. ; Roca, E. ; Fernández, F.V. ; Rodnguez-Vazquez, A.

Author_Institution

Centro Nacional de Microelectron., Inst. de Microelectron. de Sevilla, Spain

Volume

3

fYear

2000

fDate

2000

Firstpage

133

Abstract

Limitations of existing approaches for symbolic analysis of large analog circuits are discussed. To address their solution, a new methodology for hierarchical symbolic analysis is introduced. The combination of a hierarchical modeling technique and approximation strategies, comprising circuit reduction, graph-based symbolic solution of circuit equations and matrix-based error control, provides optimum results in terms of speech and quality of results

Keywords

analogue circuits; circuit analysis computing; flow graphs; symbol manipulation; approximate hierarchical symbolic analysis; approximation strategies; circuit equations; circuit reduction; error-controlled methodology; graph-based symbolic solution; large analog circuits; matrix-based error control; Analog circuits; Character generation; Circuit analysis; Circuit synthesis; Contracts; Equations; Error correction; Iterative methods; Libraries; Performance analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856014

Filename

856014