Title :
A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems
Author :
Doboli, Alex ; Dhanwada, Nagu ; Vemuri, Ranga
Author_Institution :
Dept. of Electron. Comput. & Eng. Comput. Sci., Cincinnati Univ., OH, USA
Abstract :
This paper presents a heuristic technique for automatically generating different architectures for an analog system. The AG iteratively produces various system net-lists as distinct implementations can realize the signal processing and flow in a system. Area and power for resulting net-lists are rapidly evaluated with High-Level Performance Estimator (HPE), a simplified estimation module. The AG algorithm is simple to implement. It does not require an extensive pattern library as traditional AG techniques do
Keywords :
analogue circuits; high level synthesis; signal flow graphs; analog system synthesis; heuristic technique; high-level performance estimator; net-list; signal flow graph; system-level architecture generation algorithm; Circuit synthesis; DH-HEMTs; Iterative algorithms; Libraries; Operational amplifiers; Signal design; Signal generators; Signal processing algorithms; Signal synthesis; System-level design;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.856026
