A high-speed, programmable, CSD coefficient FIR filter

Author

Zhangwen, Tang ; Zhanpeng, Zhang ; Jie, Zhang ; Hao, Min

Author_Institution

ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China

fYear

2001

fDate

2001

Firstpage

397

Lastpage

400

Abstract

A new high-speed, programmable FIR filter is present, which is a multiplierless filter with CSD encoding coefficients. With this encoding scheme, the speed of filter is improved and the area is optimized. In order to make this filter more applicable, we employ a new programmable CSD encoding structure to make CSD coefficients programmable. In the end of this paper, we design a 10-bits, 18 taps video luminance filter with the filter structure we present. The completed filter core occupies 6.8×6.8 mmm² of silicon area in Wu-Xi Shanghua 0.6 μm 2P2M CMOS technology, and its maximum work frequency is 100 MHz

Keywords

CMOS digital integrated circuits; FIR filters; high-speed integrated circuits; programmable filters; 0.6 micron; 10 bit; 100 MHz; CMOS technology; CSD encoding coefficients; high-speed programmable FIR filter; multiplierless filter; silicon area; video luminance filter; Adders; Application specific integrated circuits; CMOS technology; Delay; Encoding; Finite impulse response filter; Frequency response; Laboratories; Silicon; Student members;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982584

Filename

982584