VLSI design and architecture of a VC-Merge capable crossbar switch on MPLS over ATM

Recently, as the Internet and its services grow rapidly, a new switching mechanism, MPLS, has been introduced by IETF. In this paper, we propose a scalable hardware architecture of a high-speed crossbar switch capable of VC Merging in MPLS networks. A scheduler configuring the crossbar switch in input-queued fashion is designed and implemented. The switch has multiple queues at input ports. In the designed switch, there are eight VC-merge capable modules, one for each output port. The proposed architecture is modeled in VHDL, synthesized on SYNOPSYS, and fabricated using the SAMSUNG 0.5 μm SOG process