DocumentCode :
2226307
Title :
Design and implementation of concatenated encoder
Author :
Yu-xin, You ; Jin-xiang, Wang ; Xiu-ri, Piao ; Feng-chang, Lai ; Yi-zheng, Ye
Author_Institution :
Microelectron. Center, Harbin Inst. of Technol., China
fYear :
2001
fDate :
2001
Firstpage :
444
Lastpage :
447
Abstract :
Presented a concatenated encoder that has very wide applications in DVB, HDTV and satellite communication systems. It was mainly composed of punctured convolutional encoder, convolutional interleaver, and Reed-Solomon encoder. In the convolutional interleaver, an over-clocking scheme is employed to guarantee the speed limits. Furthermore, a finite field multiplier of composite fields was adapted to optimize area and power in RS encoder, which reduced the area near to one half compared to the conventional RS (204,188) encoder. The proposed concatenated encoder has about 3700 gates except RAM model and it has good compliance with EN300 421
Keywords :
Reed-Solomon codes; concatenated codes; convolutional codes; digital video broadcasting; high definition television; multiplying circuits; satellite communication; DVB; EN300 421; HDTV; Reed-Solomon encoder; area; composite fields; concatenated encoder; convolutional interleaver; finite field multiplier; over-clocking scheme; power; punctured convolutional encoder; satellite communication systems; Concatenated codes; Convolutional codes; Decoding; Digital video broadcasting; Error correction codes; Galois fields; Microelectronics; Polynomials; Reed-Solomon codes; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
Type :
conf
DOI :
10.1109/ICASIC.2001.982596
Filename :
982596
Link To Document :
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