DocumentCode
2226352
Title
Design of a high performance Reed-Solomon decoder with switch box control logic [HDTV]
Author
Hai-kun, Zhu ; Bo, Shen ; Qian-ling, Zhang
Author_Institution
ASIC & Syst. State-Key Lab., Fudan Univ., Shanghai, China
fYear
2001
fDate
2001
Firstpage
452
Lastpage
455
Abstract
In this paper, a pipeline Reed-Solomon decoder based on time domain decoding technique is presented. High throughput is achieved by parallel computation in the modified Euclid algorithm block, and the complex control circuit is simplified by a switch box strategy. In addition, the constant finite field multiplier is optimized to reduce the chip area, thus making the decoder suitable for HDTV
Keywords
Reed-Solomon codes; decoding; high definition television; multiplying circuits; pipeline processing; time-domain analysis; HDTV; Reed-Solomon decoder; chip area; constant finite field multiplier; modified Euclid algorithm block; parallel computation; pipeline decoder; switch box control logic; throughput; time domain decoding technique; Circuits; Computer architecture; Concurrent computing; Decoding; Error correction codes; Galois fields; Logic design; Polynomials; Reed-Solomon codes; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982598
Filename
982598
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