• DocumentCode
    2226378
  • Title

    Decrease power consumption using a programmable logic device

  • Author

    Jenkins, Jennifer

  • Author_Institution
    Xilinx Inc, San Jose, CA, USA
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    456
  • Lastpage
    461
  • Abstract
    This paper describes system design techniques using a low power CoolRunnerTM CPLD to reduce overall system power consumption. Utilizing a CoolRunner CPLD to off-load operations from the system microprocessor keeps the processor in a power saving mode longer and contributes to significant power savings
  • Keywords
    circuit CAD; integrated circuit design; logic CAD; low-power electronics; programmable logic devices; CoolRunner; low power CPLD; overall system power consumption; portable electronics; power saving mode; power savings; system design techniques; Batteries; Clocks; Energy consumption; Energy management; Logic devices; Manufacturing; Microprocessors; Power system management; Programmable logic devices; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2001. Proceedings. 4th International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    0-7803-6677-8
  • Type

    conf

  • DOI
    10.1109/ICASIC.2001.982599
  • Filename
    982599
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2226378