Title :
A novel FPGA implementation of SDH Equipment Clock
Author :
Zhou, Lianhong ; Ge, Ning ; Feng, Chongxi
Author_Institution :
Electron. Eng. Dept., Tsinghua Univ., Beijing, China
Abstract :
A novel cost-effective approach of SDH Equipment Clock (SEC) implementation is proposed in this paper. Based on FPGA and digital signal processing (DSP) algorithms as well as the theory of quantization and synthesis theory of digital phase processing, this approach brings lower noise generation, lower intrinsic output jitter, higher jitter transfer performance, excellent phase continuality as well as great flexibility. System diagram is given in the paper. Several distinct features are also discussed. Simulation and measurement results of such SEC implementation have demonstrated the feasibility of this approach
Keywords :
clocks; digital signal processing chips; field programmable gate arrays; integrated circuit noise; jitter; quantisation (signal); synchronous digital hierarchy; FPGA; SDH Equipment Clock; digital phase processing; digital signal processing algorithm; jitter transfer; noise generation; output jitter; phase continuality; quantization; synthesis theory; system diagram; Clocks; Digital signal processing; Field programmable gate arrays; Jitter; Noise generators; Phase noise; Quantization; Signal processing algorithms; Signal synthesis; Synchronous digital hierarchy;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982601
