Title :
32nm technology node Double-Gate SOI MOSFET using SiO2 gate stacks
Author :
Sangiorgi, Enrico ; Barin, Nicola ; Braccioli, Marco ; Fiegna, Claudio
Author_Institution :
ARCES, Univ. of Bologna, Bologna
fDate :
Jan. 30 2006-Feb. 1 2006
Abstract :
State of the art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the Ultra-Thin Silicon Body Double-Gate (UTB-DG) MOSFET. n-MOSFETs designed according to an original scaling strategy are simulated and the main figures of merit of the high-performance MOS transistor for digital applications are evaluated and compared to the requirements of the International Technology Roadmap for Semiconductors.The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field.
Keywords :
CMOS integrated circuits; MOSFET; silicon-on-insulator; CMOS technology; International Technology Roadmap for Semiconductors; MOS transistor; Si; SiO2; device simulation; double-gate SOI MOSFET; gate stacks; n-MOSFETs; short channel effects; silicon channel; size 32 nm; ultra-thin silicon body double-gate MOSFET; Analytical models; CMOS technology; Educational institutions; High-K gate dielectrics; Leakage current; MOSFET circuits; Quantization; Silicon; Threshold voltage; Tunneling; Double-Gate MOS; MOSFETs; Monte Carlo; Nano CMOS; device simulation; scaling;
Conference_Titel :
Nano CMOS, 2006 International Workshop on
Conference_Location :
Mishima
Print_ISBN :
978-1-4244-0603-6
DOI :
10.1109/IWNC.2006.4570975
