• DocumentCode
    2226557
  • Title

    300-MHz-frequency-band impulse-radio receiver architecture with all-digital compensation for clock jitter and frequency variation

  • Author

    Suzuki, Kenji ; Ugajin, Mamoru ; Kodate, Junichi ; Harada, Mitsuru

  • Author_Institution
    NTT Microsyst. Integration Labs., Atsugi, Japan
  • fYear
    2009
  • fDate
    Sept. 30 2009-Oct. 2 2009
  • Firstpage
    339
  • Lastpage
    342
  • Abstract
    An impulse-radio receiver architecture for the 300-MHz frequency band is presented. Digital signal processing (DSP), which compensates cycle-to-cycle jitter and frequency drift of transmitter clock, is performed in a FPGA DSP board. Owing to the process, the detection range for transmitted packets is considerably enlarged, which improves the communication range between a transmitter and receiver. A prototype wireless sensor node was developed with a fabricated IC. This sensor node, driven by a passive mechanical vibration sensor, senses the opening and closing motion of the door. The estimated lifetime of the transmitter is over ten years with a coin-sized battery.
  • Keywords
    clocks; field programmable gate arrays; jitter; ultra wideband communication; wireless sensor networks; FPGA DSP board; all-digital compensation; clock jitter; cycle-to-cycle jitter; frequency 300 MHz; frequency drift of transmitter clock; frequency variation; impulse-radio receiver architecture; passive mechanical vibration sensor; prototype wireless sensor node; Clocks; Digital signal processing; Field programmable gate arrays; Frequency; Jitter; Mechanical sensors; Prototypes; Transmitters; Vibrations; Wireless sensor networks;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radar Conference, 2009. EuRAD 2009. European
  • Conference_Location
    Rome
  • Print_ISBN
    978-1-4244-4747-3
  • Type

    conf

  • Filename
    5307194