DocumentCode
2226658
Title
Logic design on FPGA of ATM SAR function in broadband access network
Author
Qigang, Zhou ; Xiangyang, Zhu ; Lizhong, Gui ; Pengfei, Shi
Author_Institution
Shanghai Jiao Tong Univ., China
fYear
2001
fDate
2001
Firstpage
494
Lastpage
497
Abstract
The logic design on FPGAs of the ATM SAR function in broadband access networks is studied. AAL which adapts services to the ATM cell is the adaptation layer between the ATM layer and the high layer. FR and Ethernet data services should adapt the ATM cell with AAL5. Segmentation, reassembly process and traffic control issues are also discussed
Keywords
application specific integrated circuits; asynchronous transfer mode; broadband networks; field programmable gate arrays; local area networks; logic design; subscriber loops; telecommunication congestion control; AAL; AAL5; ASIC library; ATM SAR function; Ethernet data service; FPGA; FR; Xilinx XCV1000EHQ240; adaptation layer; broadband access network; data encoding block; leaky bucket parameter; logic design; reassembly process; segmentation; traffic control; Application specific integrated circuits; Asynchronous transfer mode; Electronics packaging; Ethernet networks; Field programmable gate arrays; Frame relay; Intelligent networks; Logic design; Payloads; Process control;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982608
Filename
982608
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