Title :
Efficient correlator implementation in programmable logic
Author_Institution :
Altera Eur. Technol. Centre, High Wycombe, UK
Abstract :
This paper describes a novel architecture for fast correlators, which is suitable for implementation in hardware. It combines the small size for the data processing elements of the FIR filter with the reduced memory bandwidth of the inverse FIR architecture, leading to an implementation that is superior to both for a high-speed correlator
Keywords :
FIR filters; correlators; matched filters; programmable logic devices; FIR filter; data processing; hardware design; high-speed correlator; inverse FIR architecture; matched filter; memory bandwidth; programmable logic; Correlators; Data processing; Equations; Finite impulse response filter; Hardware; Matched filters; Multiaccess communication; Programmable logic arrays; Programmable logic devices; Synchronization;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982619
