A receive path ΔΣ frequency to digital converter

Author

Filiol, N.M. ; Riley, Thomas A D ; Copeland, Miles A. ; Plett, Calvin

Author_Institution

Philsar Semicond. Inc., Nepean, Ont., Canada

Volume

3

fYear

2000

fDate

2000

Firstpage

331

Abstract

In this paper a novel architecture for a second order ΔΣ frequency-to-digital converter (FDC), aimed at receive path applications, is presented. The new architecture uses fractional-N division techniques in order to reduce the fullscale input range and out of band quantization noise when used to detect small deviation FM signals, relative to the reference frequency. The output is a single bit bitstream whose average density is an accurate representation of the instantaneous frequency deviations of the modulated IF signal

Keywords

VLSI; delta-sigma modulation; frequency modulation; interference suppression; mixed analogue-digital integrated circuits; radio receivers; ASIC; GFSK; delta-sigma convertor; fractional-N division techniques; frequency to digital converter; modulated IF signal; out of band quantization noise; quantization noise reduction; receive path ΔΣ converter; receive path applications; second order type; single bit bitstream output; small deviation FM signals; Amplitude modulation; Digital modulation; Digital-to-frequency converters; Frequency conversion; Frequency modulation; Frequency synthesizers; Inverters; Output feedback; Quantization; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856064

Filename

856064