Title :
Non-binary (7, 2)-(9, 2) parallel counters for multiplier designs
Author_Institution :
Dept. of Comput. Sci., State Univ. of New York, Geneseo, NY, USA
Abstract :
Novel non-binary parallel counters including (7, 2), (8, 2) and (9, 2), for CMOS low-power, high performance multiplier design are presented. The circuits which utilize a non-binary arithmetic scheme, possess the following unique logic features: (1) three out of four signal bits propagating through pass transistors being 0s, (2) no more than half of the signal bits subject to value-change at any logic stage, (3) high speed, good silicon layout, and minimum interconnections
Keywords :
CMOS logic circuits; VLSI; counting circuits; fixed point arithmetic; floating point arithmetic; integrated circuit design; logic design; low-power electronics; multiplying circuits; parallel processing; 0.25 micron; 2.5 V; Booth multiplier; CMOS low-power design; fixed point number multiplier; floating number multiplier; high performance multiplier design; nonBooth multiplier; nonbinary arithmetic scheme; nonbinary parallel counters; pass transistors; Arithmetic; CMOS logic circuits; Computer science; Counting circuits; Logic circuits; Logic design; Silicon; Switches; Switching circuits; Very large scale integration;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982620
