Title :
Design of a low latency high speed pipelining multiplier
Author :
Wu, Xingjun ; Chen, Hongyi ; Wei, Shaojun
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
A low latency pipelined multiplier architecture using Booth encoding technique is presented in this paper. Based on such architecture, a 16-bit multiplier, with only 5 cycles latency and about 5,000 equivalent logic gates, had been designed and integrated into the DSP core that is a key component of the four-channel CODEC chip. The chip was fabricated in 0.5 um double-poly three-metal CMOS technology. Testing results show that the multiplier can work at a more than 100 MHz clock frequency
Keywords :
CMOS digital integrated circuits; codecs; digital signal processing chips; high-speed integrated circuits; multiplying circuits; pipeline processing; 0.5 micron; 100 MHz; 16 bit; Booth encoding; CODEC chip; DSP core; double-poly three-metal CMOS technology; high-speed pipelined multiplier design; low-latency architecture; CMOS logic circuits; CMOS technology; Codecs; Delay; Digital signal processing chips; Encoding; Logic design; Logic gates; Pipeline processing; Testing;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982622
