A floating-gate pFET based CMOS programmable analog memory cell array

Author

Bragg, Julian A. ; Harrison, Reid R. ; Hasler, P. ; DeWeerth, Stephen P.

Author_Institution

Georgia Inst. of Technol., Atlanta, GA, USA

Volume

3

fYear

2000

fDate

2000

Firstpage

339

Abstract

The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off chip. Moving parameter storage on chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip non-volatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and pFET hot-electron injection to program values. With these designs, we achieve greater than 13-bit output precision with a 39 dB power supply rejection ratio and no crosstalk between memory cells

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; analogue storage; arrays; hot carriers; programmable circuits; tunnelling; CMOS analog memory cell array; addressable arrays; analog VLSI system; floating-gate MOS transistors; floating-gate p-FET; onchip nonvolatile analog memory cell; p-channel FET; pFET hot-electron injection; programmable analog memory cell array; tunneling process; Analog memory; Crosstalk; MOSFETs; Nonvolatile memory; Pins; Power supplies; Secondary generated hot electron injection; System-on-a-chip; Tunneling; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856066

Filename

856066