The use of MOS interfaces for GSI and TSI SET-based nanoelectronic processors

Summary form only given. The realization of extremely dense integrated circuits, having from 10⁹ to beyond 10¹² devices per chip presents several challenges to current I.C. fabrication technologies. Among them, power dissipation seems to be one of the most difficult hurdles to overcome. Nowadays, nanoelectronic devices seem to be an attractive alternative to MOS devices for the implementation of these GSI to TSI integrated circuits. Single electron tunneling (SET) - based transistors are well-known for their extremely low power consumption and high-scale integration capability and should be an interesting option for the implementation of extremely dense I.C.s . However, their limited driving capabilities do not favor the interfacing of SET circuits and other non-SET modules in an electronic system. In this work, the present development of circuit solutions for a GSI/TSI processor (based on single-electron transistors) that is being developed at Universidade de Brasilia will be presented. The possibilities of interfacing these SET-based circuits via MOS devices, in order to overcome the limited SET driving capabilities, will be also discussed.