Title :
Design techniques of CMOS SCL circuits for Gb/s applications
Author :
Jianhua, Lu ; Lei, Tian ; Haitao, Chen ; Tingting, Xie ; Zhiheng, Chen ; Zhigong, Wang
Author_Institution :
Dept. of Radio Eng., Southeast Univ., Nanjing, China
Abstract :
This paper presents the design techniques of Gb/s CMOS SCL circuits. Basic SCL functional cells including a 2:1 multiplexer, a D-latch, and XOR/NXOR, AND/NAND, OR/NOR gates are described in detail. Simulations show that a SCL static frequency divider can operate faster than a CMOS static logic one. Experimental results of an SCL 1:4 static frequency divider and an SCL 4:1 multiplexer both in 0.35 μm CMOS technology prove that SCL circuits can be used in Gb/s applications
Keywords :
CMOS logic circuits; flip-flops; frequency dividers; high-speed integrated circuits; integrated circuit design; logic design; logic gates; multiplexing equipment; 0.35 micron; AND/NAND gate; CMOS SCL circuit; D-latch; OR/NOR gate; XOR/NXOR gate; design technique; high-speed digital IC; multiplexer; static frequency divider; CMOS logic circuits; CMOS technology; Circuit topology; Coupling circuits; Frequency conversion; Impedance; Logic design; Logic devices; Resistors; Voltage;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982624
