DocumentCode
2227095
Title
A fast low power embedded cache memory design
Author
Xue-mei, Zhao ; Yi-zheng, Ye ; Ming-yan, Yu ; Xiao-ming, Li
Author_Institution
Microelectron. Center, Harbin Inst. of Technol., China
fYear
2001
fDate
2001
Firstpage
566
Lastpage
569
Abstract
A 64 kb cache system designed for 32 bit RISC CPU is realized. The circuits include two 4 ns 32 kb cache memories, two 1.4 ns 64-entry direct mapped translation lookaside buffers (TLB), and two 2 ns 64-lines tagRAM. The high-speed decoder and amplifier are employed. The TLB design contains a line encoder and valid bits with flash clear. This cache memory reduces the power and has faster access time by using the optimized decoder and sense amplifier. SMARCH algorithm makes all the cache system self-testability
Keywords
cache storage; embedded systems; integrated circuit design; low-power electronics; 32 bit; 64 kbit; RISC CPU; SMARCH algorithm; embedded cache memory; high-speed decoder; line encoder; low-power design; self-testability; sense amplifier; tagRAM; translation lookaside buffer; CADCAM; Cache memory; Central Processing Unit; Circuit synthesis; Computer aided manufacturing; Decoding; Delay effects; Microelectronics; Random access memory; Reduced instruction set computing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982626
Filename
982626
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