Ultra-high speed parallel multiplier with new first partial product addition algorithm

In this paper, we propose a new first partial product addition (FPA) architecture with a new compressor (or parallel counter) to the CSA tree built in the process of adding partial products for improving speed in the fast parallel multiplier. The speed of calculating partial products is improved by about 20% compared with existing parallel counters using full adders. The new circuit reduces the CLA bit finding final sum by N/2 using the novel FPA architecture. A 5.14 ns multiplication speed for a 16×16 multiplier is obtained using 0.2 μm CMOS technology. The architecture of the multiplier is easily adapted for pipeline design and demonstrates high speed performance