Building blocks for large annealed compact neural networks

Author

Laiho, Mika ; Paasio, Ari ; Halonen, Kari

Author_Institution

Lab. of Electron. Circuit Design, Helsinki Univ. of Technol., Espoo, Finland

Volume

3

fYear

2000

fDate

2000

Firstpage

415

Abstract

In this paper the design issues of large globally connected compact neural networks are targeted. Building blocks of a cell that is capable of performing the hardware annealing function are designed. Different offset compensation schemes are used to eliminate the offset currents. The cell is designed to have voltage outputs to facilitate the interconnecting of cells. The blocks are processed with a 0.5 μm standard digital CMOS process and measurement results of selected building blocks of the cell are included

Keywords

CMOS digital integrated circuits; cellular neural nets; error compensation; integrated circuit design; neural chips; 0.5 micron; CNN; building blocks; cell voltage outputs; design issues; digital CMOS process; globally connected neural networks; hardware annealing function; large annealed compact neural networks; offset compensation schemes; offset currents; Annealing; Cellular neural networks; Decoding; Electronic circuits; Hardware; Integrated circuit interconnections; Laboratories; Multiaccess communication; Neural networks; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856085

Filename

856085