A high performance MAC design using proposed low power IP-cells

Author

Lee, Seung-Min ; Seung-Min Lee

Author_Institution

Dept. of Inf. & Commun. Eng., Dongshin Univ., Chonnam, South Korea

fYear

2001

fDate

2001

Firstpage

596

Lastpage

598

Abstract

In this paper, a study is presented on High Speed (HS) and 59 mW Low Power (LP) 16×16 MAC performance of new XOR-based circuits using transmission gate (TG) logic implemented in 0.25 μm CMOS SLP/5LM technology. It is shown that our proposed MAC results in better performance than other published MACs due to the lack of DC leakage currents for low power and the elimination of unnecessary switching activities with latches before and after multipliers for high speed

Keywords

CMOS logic circuits; application specific integrated circuits; high-speed integrated circuits; integrated circuit design; low-power electronics; multimedia computing; multiplying circuits; 0.25 micron; 59 mW; CMOS SLP/5LM technology; DC leakage currents; XOR-based circuits; high performance MAC design; high speed low power 16×16 MAC performance; latches; low power IP-cells; multiplier-accumulator macro; real time multimedia system; switching activity bypassing; transmission gate logic; Adders; CMOS logic circuits; CMOS technology; Digital signal processing; Hardware design languages; Logic design; Logic gates; Multimedia systems; Real time systems; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982634

Filename

982634