An approach to reducing power consumption during delay test application

Author

Li, Xiaowei ; Li, Huawei ; Luo, Zuying ; Min, Yinghua

Author_Institution

Inst. of Comput. Technol., Acad. Sinica, Beijing, China

fYear

2001

fDate

2001

Firstpage

620

Lastpage

623

Abstract

This paper presents an approach to reducing power consumption during delay test application. It is based on a re-ordering of the test-pairs in the test sequences to minimize the switching activity of the circuit-under-test during test application. Hamming distance between test-pairs is used to guide test-pair re-ordering. This guarantees a decrease in power consumption without reducing delay fault coverage. Experimental results are presented to demonstrate a reduction of the circuit activity for an average of 90.78% during test application

Keywords

CMOS logic circuits; Hamming codes; automatic testing; delays; fault diagnosis; integrated circuit testing; logic gates; logic testing; low-power electronics; CMOS; Hamming distance; benchmarks; circuit activity; circuit-under-test; delay fault coverage; delay test application; gate identifiers; power consumption; switching activity; test application; test sequences; test-pairs re-ordering; Benchmark testing; Circuit faults; Circuit testing; Computers; Costs; Delay; Energy consumption; Hamming distance; Logic; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982640

Filename

982640