DocumentCode
2227737
Title
A new low power BIST methodology by altering the structure of linear feedback shift registers
Author
Li, Rui ; Hu, Chen ; Yang, Jun ; Zhang, Zhe ; Shi, Youhua ; Shi, Longxing
Author_Institution
Nat. ASIC Syst. Eng. Center, Southeast Univ., Nanjing, China
fYear
2001
fDate
2001
Firstpage
646
Lastpage
649
Abstract
In this paper a new low power BIST methodology effected by altering the structure of linear feedback shift register (LFSR) is proposed. In pseudo-random test mode, the efficiency of the vectors decreases sharply as the test progresses. For low power consumption during test mode, the proposed approach ignores the nondetecting vectors by altering the structure of LFSR. Note that altering the structure of LFSR is efficient, and it has no impact on the fault coverage
Keywords
built-in self test; circuit feedback; fault diagnosis; logic testing; low-power electronics; sequential circuits; shift registers; BIST; fault coverage; linear feedback shift registers; low power consumption; low power methodology; pseudo-random test mode; transition logic; Application specific integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Energy consumption; Linear feedback shift registers; Logic; Power dissipation; Read only memory; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982646
Filename
982646
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