Title :
A new software for test logic optimization in DFT
Author :
Zhang, Zhe ; Hu, Chen ; Li, Rui ; Shi, Youhua ; Shi, Longxing
Author_Institution :
Nat. ASIC Syst. Eng. Center, Southeast Univ., Nanjing, China
Abstract :
This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: test analysis module and DFT module. Test analysis module can examine a circuit´s testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment with ASIC2000TA is presented
Keywords :
application specific integrated circuits; boundary scan testing; circuit optimisation; circuit simulation; design for testability; electronic data interchange; fault simulation; logic testing; ASIC2000TA; Cadence; DFT; electronic design intermediate format; fault simulation; full scan; gate-level netlist; greedy search algorithm; partial scan; test analysis module; test logic; test logic optimization; test vectors; Algorithm design and analysis; Circuit faults; Circuit testing; Design for testability; Design optimization; Logic design; Logic testing; Performance analysis; Performance evaluation; Software testing;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982648
