Title :
QFP package analysis using partial element equivalent circuits
Author :
Jiang, Qifeng ; Cao, Yi ; Li, Zhengfan
Author_Institution :
Shanghai Jiao Tong Univ., China
Abstract :
The partial element equivalent circuit (PEEC) technique is employed to model the electrical properties of the generic 64-lead quad-flat-pack (QFP). The model for the package includes many details, such as the leads, bonding wires and finite-size dielectrics. This model is used to investigate the parasitic effect of the package. As an example, the equivalent circuit is used to simulate the simultaneous switching noise (SSN) in conjunction with the devices on the chip
Keywords :
equivalent circuits; integrated circuit modelling; integrated circuit noise; integrated circuit packaging; lead bonding; 64-lead quad-flat-pack; PEEC technique; QFP package analysis; bonding wires; electrical properties modeling; finite-size dielectrics; leads; package parasitic effect; partial element equivalent circuits; simultaneous switching noise; Bonding; Circuit simulation; Conductors; Coupling circuits; Dielectrics; Electronics packaging; Equivalent circuits; Geometry; Lead; Wires;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982656
