A hierarchical circuit extraction based on scan line

Author

Gu, Xiaoyun ; Chen, Shuilong ; He, Xiangqing

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2001

fDate

2001

Firstpage

689

Lastpage

692

Abstract

A method for hierarchical layout circuit extraction is presented. It uses double scan lines method to search for overlapping area between instances and physical layers, analyze the connectivity between the layers to obtain the transistors and the nets. This analysis is done from the bottom up, after obtaining the connectivity, it merges the nets connected through instances and obtains the correct hierarchical nets connection using a bottom up net search technique. The algorithm uses the properties of overlapping and the time to process overlapping is saved, it can process complex overlaps between instances, instance and geometry and also can be applied to layout extraction with large hierarchical level effectively. By using this method, the hierarchical net results can be obtained properly and efficiently

Keywords

VLSI; circuit layout CAD; integrated circuit layout; IC layout; VLSI circuit design; bottom up net search technique; connectivity analysis; double scan lines method; hierarchical layout circuit extraction; net merge technique; overlapping area; Circuits; Data mining; Design methodology; Geometry; Helium; Information analysis; MOS devices; Microelectronics; Physical layer; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982657

Filename

982657