Title :
Proceedings of 33rd Design Automation Conference
Abstract :
The following topics were dealt with: high speed interconnect; power analysis; high level synthesis; asynchronous circuits analysis and synthesis; new frontiers in partitioning; trends in verification; test and fault tolerance in high level synthesis; discrete simulation; design environments; combinational logic synthesis; pattern generation for test and diagnosis; CAD for analog and mixed signal ICs; design for testability; electrical simulation; mixed signal design; functional verification of microprocessors; 3D parasitic extraction; routing optimisation for performance; power estimation; hardware-software codesign; verification of sequential systems; embedded software analysis and compilation; layout analysis and optimisation; hardware description language techniques; power minimisation in IC design; and technology optimisation for cells and systems
Keywords :
circuit layout CAD; 3D parasitic extraction; IC design; asynchronous circuits analysis; combinational logic synthesis; compilation; design environments; design for testability; discrete simulation; electrical simulation; embedded software analysis; fault tolerance; functional verification; hardware description language techniques; hardware-software codesign; high level synthesis; high speed interconnect; layout analysis; microprocessors; mixed signal design; optimisation; partitioning; pattern generation; power analysis; power estimation; power minimisation; routing optimisation; sequential systems; technology optimisation; verification;
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV, USA
Print_ISBN :
0-7803-3294-6
DOI :
10.1109/DAC.1996.545534
