DocumentCode :
2228134
Title :
Hierarchical h-adaptive computation in VLSI interconnect capacitance extraction
Author :
Lu, Taotao ; Wang, Guanghui ; Wang, Zeyi
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear :
2001
fDate :
2001
Firstpage :
712
Lastpage :
715
Abstract :
A hierarchical h-adaptive method based on BEM is proposed for VLSI parasitic capacitance extraction. In h-adaptive methods, high computational accuracy is guaranteed by auto refinement of the boundary elements. A new auto refinement method is introduced by property storage of the boundary elements. It is more effective than the old methods in the stability of adaptive computation. A new error estimator based on superconvergent recovery technology is presented, to determine which of the elements should be refined. Numerical results show that adaptive computation using the new auto element refinement and error estimator is very effective both in accuracy and speed
Keywords :
VLSI; boundary-elements methods; capacitance; error analysis; integrated circuit interconnections; integrated circuit modelling; numerical stability; BEM; VLSI interconnect capacitance extraction; adaptive computation stability; boundary elements auto refinement; computational accuracy; deep sub-micron IC design; error estimator; hierarchical h-adaptive method; numerical results; superconvergent recovery technology; Circuit optimization; Computer science; Delay; Integrated circuit interconnections; Integrated circuit technology; Interpolation; Laplace equations; Parasitic capacitance; Stability; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
Type :
conf
DOI :
10.1109/ICASIC.2001.982663
Filename :
982663
Link To Document :
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