Title :
A design methodology of vector unit for Emotion synthesis
Author_Institution :
Syst. LSI Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
With advances in silicon technology and system integration technology, utmost care for RC-delay must be taken in high performance LSI design. This paper presents the design method applied to the vector unit (VU) implemented in PlayStation(R)-2 CPU, called the ´Emotion Engine´. This paper presents our design method which can estimate wire load by predicting wire shape, and the estimated RC delay is effectively used for pre-layout timing analysis. The method enables us to obtain accurate pre-layout timing result and reduce the design turn-around time. With this method, the VU has achieved an operating frequency of 300 MHz and 2.24 Giga floating operation per seconds (GFLOPS)
Keywords :
CMOS digital integrated circuits; computer graphic equipment; delay estimation; digital signal processing chips; floating point arithmetic; integrated circuit layout; pipeline processing; timing; vector processor systems; 2.24 GFLOPS; 3-D graphics engine; 300 MHz; CMOS technology; Emotion Engine; PlayStation-2 CPU; RC-delay; design methodology; design turn-around time; floating point vector calculations; high performance LS1 design; operating frequency; prelayout timing analysis; vector calculation engine; vector unit; wire load; wire shape; Delay effects; Delay estimation; Design methodology; Engines; Frequency; Large scale integration; Shape; Silicon; Timing; Wire;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982667
