DocumentCode :
2228346
Title :
Parameterized IP core design
Author :
Junchao, Zhao ; Weiliang, Chen ; Shaojun, Wei
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fYear :
2001
fDate :
2001
Firstpage :
744
Lastpage :
747
Abstract :
In the era of Systems-on-Chip (SoC), in order to reduce product cycle time and development cost, people have developed an IP-based SoC design methodology. However, this new methodology raises more issues for IP core creation. In order to make an IP core more flexible for SoC, the core should be configurable. Such configurability requires a new focus on "parameterized IP core". In this paper, we describe the IP core reconfiguration mechanism, define two main types of IP core parameters (static parameters and dynamic parameters), and focus on parameterization, one proposed solution to IP core reconfiguration
Keywords :
application specific integrated circuits; hardware description languages; industrial property; integrated circuit design; reconfigurable architectures; HDL level; IP core creation; IP core reconfiguration mechanism; SoC design methodology; configurable core; dynamic parameters; parameterized IP core design; product cycle time; product development cost; static parameters; system-on-chip; Buildings; Chip scale packaging; Costs; Design methodology; Flexible printed circuits; Hardware design languages; Intellectual property; Microelectronics; Qualifications; Relays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
Type :
conf
DOI :
10.1109/ICASIC.2001.982670
Filename :
982670
Link To Document :
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