Title :
A scalable test mechanism and its optimization for test access to embedded cores
Author :
Hu, He ; Yihe, Sun
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
In this paper, a test access mechanism named TESTLINE and its test time and power optimization algorithm for SOC test is presented. TESTLINE just needs 5 pins and can provide high-speed parallel test scheme. TESTLINE has a scalable mechanism. Its schematic can be easily configured according to test time and test power. ILP (Integer Linear Programming) is used to find the optimal results. TESTLINE also is a hierarchical structure. It is easy to build a hierarchical test access mechanism
Keywords :
VLSI; automatic test equipment; automatic testing; design for testability; embedded systems; hierarchical systems; integer programming; integrated circuit testing; optimisation; Integer Linear Programming; TESTLINE; embedded cores; hierarchical structure; hierarchical test access; high-speed parallel test; power optimization algorithm; scalable mechanism; test access; Automatic testing; Bandwidth; Built-in self-test; Circuit testing; Costs; Helium; Integer linear programming; Microelectronics; Pins; Silicon;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982677
