A modified microprogramming control for FPU

Author

Zheng, Liang ; Xu-Bang, Shen ; Xiao-Ji, Wang

Author_Institution

Xi´´an Inst. of Microelectron. Technol., China

fYear

2001

fDate

2001

Firstpage

789

Lastpage

792

Abstract

A novel architecture and control of the FPU LSC87 chip, which is instruction compatible with INTEL 8087 coprocessors, is described. The modified microprogramming control presented here is best suited for complicated processes, including the supporting of 7 floating point numbers and binary or decimal integers, the implementation of IEEE standard 754 floating point arithmetic, as well as the computation of transcendental functions, especially the 6 internal exceptions affected by the execution of LSC87 instructions and the corresponding masked and unmasked exception handling. To accelerate the execution of computation instruction, the hardwired control is combined with a microprogramming approach. The control unit completed in LSC87 simplifies the architecture design, expedites FPU development and saves area cost

Keywords

CMOS digital integrated circuits; coprocessors; exception handling; floating point arithmetic; integrated circuit layout; microprogramming; CMOS library; FPU LSC87 coprocessor; IEEE standard 754 floating point arithmetic; Intel 8087 coprocessor compatibility; architecture design; binary integers; custom design; decimal integers; floating point numbers; hardwired control; instruction compatibility; masked exception handling; modified microprogramming control; transcendental functions; unmasked exception handling; Acceleration; Communication system control; Computer aided instruction; Computer architecture; Coprocessors; Costs; Electronic mail; Microelectronics; Microprogramming; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982681

Filename

982681