Design and VLSI implementation of an asynchronous low power microcontroller

A novel VLSI design and implementation of a low power 8-bit microcontroller using asynchronous logic is proposed in this paper. Taking advantage of the low power potential of asynchronous logic, the 2-stage pipelined MCU is carefully designed by chosen proper architecture as well as suitable asynchronous signal protocols which including a combination of a specific "Completion Detection Method" and "matching delay Method". Other low power design techniques such as "Gating Clock" also applied to the design. Using synchronous design flow and standard-cell library facilitates the VLSI design and circuit implementation. Fabricated in Chartered 0.6 um CMOS technology, this low power asynchronous MCU achieves only 16% power dissipation of the conventional designed PIC16C61, which shares the same instruction set and function as the MCU we designed