• DocumentCode
    2228691
  • Title

    An open-loop full CMOS 103 MHz -61 dB THD S/H circuit

  • Author

    Hadidi, Khayrollah ; Sasaki, Masahiro ; Watanabe, Tadatoshi ; Muramatsu, Daigo ; Matsumoto, Takashi

  • Author_Institution
    Dept. of Electr. Eng., Urmia Univ., Iran
  • fYear
    1998
  • fDate
    11-14 May 1998
  • Firstpage
    381
  • Lastpage
    383
  • Abstract
    Based on a real open loop architecture and a cascode-driver CMOS source-follower, we implemented a S/H circuit in a 0.8 μm digital CMOS process. The circuit achieved -61 dB THD at a sampling rate of 103 MHz, while a 1.42 Vp-p 10 MHz input signal was applied. This includes all parasitic loading and transient effects
  • Keywords
    CMOS analogue integrated circuits; harmonic distortion; sample and hold circuits; transients; 0.8 micron; 103 MHz; THD; cascode-driver CMOS source-follower; open-loop full CMOS S/H circuit; parasitic loading; sampling rate; transient effects; CMOS process; CMOS technology; Clocks; Feedback circuits; Frequency; Linearity; Sampling methods; Signal sampling; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
  • Conference_Location
    Santa Clara, CA
  • Print_ISBN
    0-7803-4292-5
  • Type

    conf

  • DOI
    10.1109/CICC.1998.695004
  • Filename
    695004
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2228691