Title :
A 1 GHz analog multiplier with shunt-peaked LNA core
Author :
Xu, Donglin ; Zhang, Jie ; Ren, Junyan
Author_Institution :
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
Abstract :
A 1 GHz analog multiplier with a supply of 1.2 V is implemented with a 0.6 micron DPDM standard CMOS technology of CSMC, China. With a shunt-peaked, low noise amplifier (LNA) core, the proposed multiplier features with IIP3 of 6.3 dBm (for mixer application), conversion gain of 10 dB and noise figure of 18 dB with a power consumption of 22 mW. Several design techniques have been adopted to achieve the target of low noise, low power and high speed. This multiplier can be used as the basic element of a RF mixer
Keywords :
CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; UHF mixers; analogue multipliers; high-speed integrated circuits; integrated circuit design; integrated circuit noise; low-power electronics; 0.6 micron; 1 GHz; 1.2 V; 10 dB; 18 dB; 22 mW; CMOS technology; IIP3; RF mixer; analog multiplier; conversion gain; low-power high-speed design; noise figure; power consumption; shunt-peaked LNA core; Bandwidth; CMOS technology; Circuit noise; Impedance; Inductance; Low-noise amplifiers; Noise figure; Radio frequency; Resonance; Voltage;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982686
