Title :
A 3.3-V, 2-GHz CMOS low noise amplifier
Author :
Zhao, Hui ; Ren, Junyan ; Zhang, Qianling
Author_Institution :
ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China
Abstract :
A CMOS low noise amplifier is designed based on a narrowband LC-tuned cascode topology. With a standard 0.6 micron CMOS technology, this technique is applied to design a 3.3 V LNA operating at 2 GHz for IMT2000 band application. On-chip inductors have been used. Simulation results show that the LNA is featured with a gain of 18 dB, noise figure of 2.3 dB, IIP3 of -4.9 dBm, power dissipation of 33.9 mW, and well-matched inputs
Keywords :
CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; integrated circuit design; integrated circuit noise; low-power electronics; 0.6 micron; 18 dB; 2 GHz; 2.3 dB; 3.3 V; 33.9 mW; CMOS low noise amplifier; IIP3; IMT2000 band; gain; input matching; low power RFIC design; narrowband LC-tuned cascode topology; noise figure; on-chip inductor; power dissipation; CMOS technology; Circuit noise; Inductors; Low-noise amplifiers; Narrowband; Noise figure; Power dissipation; RF signals; Radio frequency; Transceivers;
Conference_Titel :
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6677-8
DOI :
10.1109/ICASIC.2001.982688
