Title :
The performance model of Hyper-Threading Technology in Intel Nehalem microarchitecture
Author :
Tian, Yuan ; Lin, Chuang ; Hu, Kangqiao
Author_Institution :
Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
The Hyper-Threading Technology introduced by Intel makes one physical processor appear as two logical processors with duplicated architecture state and shared system resources. From microarchitecture perspective, instructions from both logical processes will execute simultaneously by competing shared resources. This paper proposes a novel Generalized Stochastic Petri Nets (GSPN) model for the Hyper-Threading Technology which is well-suited to model the synchronization, parallelization, buffering and resource sharing. We set accurate input parameters depending on the characters of applications running on the processors which allow us to predict performance precisely. We compare our results of model simulation with the outcome of experiments on Intel Nehalem-EP series processors and it shows our model produces less than 10% error rate for the CPI and the use states of IQ, RS, ROB.
Keywords :
Petri nets; multi-threading; HTT; Intel Nehalem microarchitecture; buffering; generalized stochastic Petri net model; hyperthreading technology; logical processor; parallelization; performance model; physical processor; resource sharing; shared system resource; Annealing; Artificial intelligence; Bandwidth; Facial animation; Microarchitecture; Table lookup; GSPN; Hyper-Threading Technology; out-of-order; pipeline;
Conference_Titel :
Advanced Computer Theory and Engineering (ICACTE), 2010 3rd International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-6539-2
DOI :
10.1109/ICACTE.2010.5579564