POSE: power optimization and synthesis environment

Author

Iman, Sasan ; Pedram, Massoud

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

1996

fDate

3-7 Jun, 1996

Firstpage

21

Lastpage

26

Abstract

Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and academia with an environment and tool suite for automatic synthesis and optimization of low power circuits. POSE provides a unified framework for specifying and maintaining power relevant circuit information and means of estimating power consumption of a circuit using different load models. POSE also gives a set of options for making area-power trade-offs during logic optimization

Keywords

CMOS digital integrated circuits; circuit CAD; circuit optimisation; integrated circuit design; integrated circuit modelling; logic design; POSE; area-power trade-offs; automatic synthesis; digital CMOS circuits; logic optimization; low power circuits; power optimization; power relevant circuit information; tool suite; Circuit synthesis; Contracts; Design automation; Design optimization; Digital systems; Electronics industry; Energy consumption; Logic; Permission; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference Proceedings 1996, 33rd

Conference_Location

Las Vegas, NV

ISSN

0738-100X

Print_ISBN

0-7803-3294-6

Type

conf

DOI

10.1109/DAC.1996.545538

Filename

545538