Memory and logic integration for System-in-a-Package

Author

Wang, Michael ; Suzuki, Katsuharu ; Sakai, Atsushi ; Dai, Wayne

Author_Institution

Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA

fYear

2001

fDate

2001

Firstpage

843

Lastpage

847

Abstract

System-in-a-Package (SiP), a generalization of System-on-a-Chip (SoC), provides a cost-effective solution for large-scale memory and logic integration and an attractive alternative for embedded memory. The key elements of SiP memory/logic integration technology include IO redistribution; solder bumping; and flip chip assembly. Two SiP platforms: Chip-on-Chip technology and Chip-Laminate-Chip technology are introduced in this paper. An innovative configurable area-IO memory architecture for System-in-a-Package is presented. A 512 K SRAM chip has been designed to verify this approach

Keywords

SRAM chips; embedded systems; flip-chip devices; integrated circuit packaging; integrated logic circuits; soldering; 512 Kbyte; Chip-Laminate-Chip technology; Chip-on-Chip technology; IO redistribution; SRAM chip; System-in-a-Package; configurable area-IO memory architecture; embedded memory; flip-chip assembly; memory/logic integration technology; solder bumping; Assembly; CMOS technology; Costs; Fabrication; Flip chip; Logic; Memory architecture; Packaging; Random access memory; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982696

Filename

982696