CMOS APS ASIC testing and evaluation

An ASIC CMOS image Active Pixel Sensor (APS) with combined linear and logarithmic modes of operation is presented. The chip consists of a 64 x 64 pixel array, together with its digital control and timing circuits. Test structures including individual photodiodes and pixels are also integrated for characterization purpose. The chip features selectable linear and logarithmic modes of operation, digitally controlled integration time, and correlated double sampling (CDS) circuit for readout. The chip was designed and fabricated using a 0.6 μm CMOS process. The experimental results obtainedfrom the chip are presented in this paper.