Title :
Process dependent static cache partitioning for real-time systems
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie-Mellon Univ., Pittsburgh, PA, USA
Abstract :
The author investigates the use of a priori knowledge of program behavior to partition an instruction cache of size C into a static partition of size S and an LRU partition of size C -S. The value of S is task-dependent and is nonzero for most programs running on the system. Example programs are presented, and their behavior in various size caches is discussed. Cache partitions are generated and evaluated to determine the increase in cache performance and predictability. A high-level hardware design is presented that provides the desired partitioning scheme
Keywords :
buffer storage; real-time systems; LRU partition; a priori knowledge; cache performance; high-level hardware design; instruction cache; predictability; process dependent static cache partitioning; program behavior; real-time systems; Algorithm design and analysis; Cache memory; Computer architecture; Costs; Data structures; Hardware; Kirk field collapse effect; Processor scheduling; Real time systems; Scheduling algorithm;
Conference_Titel :
Real-Time Systems Symposium, 1988., Proceedings.
Conference_Location :
Huntsville, AL
Print_ISBN :
0-8186-4894-5
DOI :
10.1109/REAL.1988.51114
