DocumentCode :
2229446
Title :
Behavioral synthesis
Author :
Camposano, Raul
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
fYear :
1996
fDate :
3-7 Jun, 1996
Firstpage :
33
Lastpage :
34
Abstract :
Since the 1988 tutorial on behavioral (high-level) synthesis which appeared in the DAC proceedings (and later in the proceedings of the IEEE) much has happened in the field. Behavioral synthesis is now considered mainstream EDA as evidenced by the number of articles at conferences, journals and books. May be even more significant, several products are being offered commercially, and the number of designers using behavioral synthesis is probably in the hundreds. The initial promise of behavioral synthesis, to dramatically increase productivity by elevating the level of design, has been fulfilled. The increase in productivity of behavioral design versus RTL design is typically quoted at 5 times. What came as a surprise to most researchers in the field, is that this is achieved without impacting the quality of results (area, timing)! If anything, behavioral designs are slightly smaller and faster that their RTL counterparts, mainly because much more architectural exploration can be afforded at the behavioral level, thus providing a better starting point for synthesis
Keywords :
circuit optimisation; high level synthesis; logic CAD; reviews; architectural exploration; behavioral synthesis; high-level synthesis; low power circuits; productivity; Algorithm design and analysis; Application software; Books; Digital signal processing; Electronic design automation and methodology; Logic; Permission; Productivity; Registers; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
ISSN :
0738-100X
Print_ISBN :
0-7803-3294-6
Type :
conf
DOI :
10.1109/DAC.1996.545540
Filename :
545540
Link To Document :
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